With continuous development in semiconductor technologies, the performance improvement of integrated circuits is mainly achieved by continuously reducing dimensions of the integrated circuit devices to increase their speeds. Currently, due to high device density, high performance, low cost in semiconductor processes and advancements to process nodes of nanotechnologies, the fabrication of semiconductor devices is limited by various physical limits.
With continuous reduction of dimensions of complementary metal-oxide-semiconductor (CMOS) devices, challenges from their manufacturing and design promote the developments of three-dimensional designs such as fin field effect transistors (FinFETs). Compared with conventional planar transistors, the fin field effect transistors have superior performance in channel control and reduction of the shallow channel effect. Planar gate structures are set above the channels, while gate structures of the fin field effect transistors surround the fins. In such way, the static electricity can be controlled from three directions in the fin field effect transistors, which have superior performance in terms of electrostatic control.
However, the fin field effect transistors have a serious self-heating effect. The disclosed devices and methods are directed to at least partially alleviate one or more problems set forth above and to solve other problems in the art.